Jiwon Jo (Combined Graduate Student)
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Graduate Student (M.S), Embedded System-on-Chip Integrator |
Repository Commit History
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Introduction
Full Bio Sketch
Mr. Jo is currently pursuing his undergraduate degree in Electronics Engineering at Kyungpook National University, Daegu, Republic of Korea. His research interests focus on hardware-software co-design, including System-on-Chip (SoC) architectures, embedded systems, edge computing systems, and AI accelerators. He has worked on RISC-V processor implementation, RTL-based hardware design, and the design of streaming-based concurrent CNN accelerator architectures. His current research focuses on improving system performance and resource utilization by exploiting runtime execution characteristics and addressing memory bottlenecks.
Research Topic
Compact CPU-Integrated CNN Acceleration Architecture by Streamlining Memory Access for Concurrent Neural Processing
Convolutional Neural Networks (CNNs) require intensive computation and frequent memory access, which can lead to significant performance bottlenecks in resource-constrained systems. To address these challenges, this study proposes a compact RISC-V-based CNN accelerator integrated with a CPU as a co-processor. The proposed architecture reduces memory overhead through a streaming-based dataflow and on-the-fly data generation while enabling continuous neural processing with a compact buffer structure. The accelerator employs weight-stationary systolic arrays and loosely coupled controllers to improve data reuse and overlap memory access with computation. By allowing the CPU and accelerator to operate concurrently, the proposed design improves computational efficiency while reducing memory access costs. This work focuses on efficient hardware architectures for AI acceleration, particularly in systems where memory bandwidth and resource utilization are critical design constraints.
Runtime Feedback-based Adaptive Skip Policy for Efficient CNN Inference
This study focuses on a runtime feedback-based adaptive skip policy for efficient convolutional neural network inference. Using MobileNetV2 as a case study, it analyzes intermediate feature representations and prediction confidence to determine when computation can be selectively skipped. The policy uses runtime feedback to adapt skip decisions according to input behavior, aiming to reduce computation while maintaining prediction consistency under varying input conditions.
Publications
Journal Publications (SCI 0, KCI 0)
Conference Publications (Intl. 1)
Jiwon Jo and Daejin Park. Compact CPU-Integrated CNN Acceleration Architecture by Streamlining Memory Access for Concurrent Neural Processing In IEEE COOLChips 2026, 2026.
Participation in International Conference
IEEE COOLChips 2026, Tokyo, Japan
Last Updated, 2026.07.06
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