Hoseung Kim (Integrated Ph.D Student)
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Undergraduate Student (B.S), Embedded System-on-Chip Integrator |
Repository Commit History
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Introduction
Full Bio Sketch
Mr. Kim is currently doing his undergraduate degree in Electronics Engineering at KyungBook National University, Daegu, republic of Korea. His research interests design efficient(low power, high speed accelerator) microprocessor architecture for AI and various computing applications, specially design in effective and powerful parallel processing data structure for AI and multi task using multi-core structure based on RISC-V. He is pursuing this research to apply specializly purposed embedded system on chip from customized small scale application(IOT) to large scale application(big data processing computer). Furthermore, He is seeking flexible Hardware-software friendly structure and algorithm to design powerfully optimized system on chip.
Research Topic
low power high speed CNN accelerator with matrix reordering techniques for small footprint memory access
In artificial intelligent and big data era, enormous data volumes are used to information expression. the property of this information is multi-dimension structure data set, it can be expressed by matrix or tensor. So various data elements are simultaneously processed at once. With ordinary sequential processing way computer structure, this huge amount of information processing takes too much time and has high order time complexity.
For efficient matrix/tensor data set processing, used parallelism and independence matrix arithmetic property, matrix operation can be conducted in parallel processing way. By implementing processing unit and memory structure conducted this method, compared to sequential processing way, the number of iterative memory access sequence and ALU operations of same data elements can be drastically reduced. These characteristics naturally can decrease the power consumption of system and increase the operation performance used this hardware module.
Furthermore, embedded system software of this hardware module and developed new compile method, such as pruning, key data extraction, and matrix data compression conceptions, it is possible to minimize the size of data to be processed in advance. So, this algorithm can accelerate and lessen burden hardware processing information data volumes in compile, preprocessing, and operation step. This can eventually enable the minimized hardware module implementation and improve the hardware operation performance.
As a result, High speed and low memory access footprint but low power consumption, namely, highly efficient system module chip for matrix operation can be implemented. This chip is based on RISC-V, this can easily fit in existing hardware board. So, widely used in various situation and hardware device, where huge volumes of matrix/tensor data process needed.
Publications
Conference Publications
Hoseung Kim and Daejin Park. Low-Power High Speed CNN Accelerator with Matrix Reordering Techniques for Small Footprint Memory Access (Under Review) In IEEE International Conference on Artificial Intelligence in Information and Communication (ICAIIC 2025), 2025.
Hoseung Kim and Daejin Park. Preparing IEEE COOLChips, 2025.
Hoseung Kim and Daejin Park. Preparing IEEE ISOCC, 2025.
Participation in International Conference
IEEE ICAIIC 2025, Fukuoka, Japan
IEEE COOLChips 2025, Tokyo, Japan
IEEE ISOCC 2025, Busan, Korea
Last Updated, 2024.12.13
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