Hyunjae Kim (Combined Graduate Student)
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Graduate Student (M.S), Embedded System-on-Chip Integrator |
Repository Commit History
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Introduction
Full Bio Sketch
Mr. Kim is currently pursuing his undergraduate degree in Electronics Engineering at Kyungpook National University, Daegu, Republic of Korea. His research interests focus on embedded systems, computer architecture, parallel/concurrent processor design, and hardware/software co-design for efficient data processing systems. He have worked on RISC-V processor implementation, FPGA/RTL-based hardware design, and LiDAR data processing architectures for adaptive cruise control systems. His current research interests focus on efficient processor and accelerator architectures, memory hierarchy optimization, and real-time embedded computing system.
Research Topic
Direct Sparse LiDAR Streaming for Profile-Adaptive ACC
LiDAR-based adaptive cruise control (ACC) requires real-time processing of large spatial sensor data, but storing and processing all LiDAR samples as dense frames can introduce significant input staging and memory-access overhead. My research focuses on a CPU-accelerator co-design architecture that validates and quantizes incoming LiDAR distance samples before dense-frame storage, packetizes only valid samples into 4×4 sparse tile packets, and streams them directly to the accelerator.
The accelerator performs tile-level pooling, object-slot tracking, and side-static filtering to generate compact object metadata such as bounding boxes, object counts, and representative distance information. The metadata is exposed to the CPU through MMIO registers, enabling metadata-based ACC policy without directly processing the full LiDAR frame. This structure also supports frame-latched profile-adaptive execution, allowing different quantization settings and processing profiles to be applied according to driving conditions while maintaining deterministic frame-level behavior.
Future Research Interests
My future research interests lie in memory-efficient processor and accelerator architectures for real-time embedded systems. Building on my previous experience with sparse sensor data processing and streaming-based accelerator design, I would like to further explore memory bottleneck reduction, data-movement-aware architecture, and memory hierarchy optimization.
One direction I am particularly interested in is improving how processors and accelerators manage short-lived intermediate data. In many streaming, parallel, and intelligent workloads, data is often produced, consumed, and discarded within a short execution window. I hope to explore lightweight architectural mechanisms that can reduce unnecessary movement of such data through conventional cache and memory hierarchies, for example by adapting buffering, forwarding, or data placement strategies according to data lifetime and reuse patterns.
I am also interested in parallel and multithreaded hardware architectures that improve throughput and hide memory access latency through efficient parallel execution, synchronization, and resource management. By combining memory-aware design, accelerator architecture, and parallel processing, I hope to develop efficient computing systems
Publications
Journal Publications (SCI 0, KCI 0)
Conference Publications (Intl. 2)
Hyunjae Kim and Daejin Park. Under Blind Review In IEEE APCCAS 2026, 2026.
Hyunjae Kim and Daejin Park. Under Blind Review In IEEE A-SSCC 2026, 2026.
Participation in International Conference
IEEE IPFA 2026, Singapore, Singapore
IEEE APCCAS 2026, Fukuoka, Japan
IEEE A-SSCC 2026, Taipei, Taiwan
Last Updated, 2026.07.13
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